1. Field of the Invention
The present invention relates to a memory system, and more particularly, to an improved memory access circuit (addressing circuit) used in a digital data processing system in which a large amount of data are handled.
2. Description of the Prior Art
In the digital data processing field, the amount of data to be handled has remarkably increased with improvements in data processing techniques. Therefore, of particular interest in the digital data processing field is how quickly a large amount of data can be processed.
A memory is invariably employed in digital data processing. Digital data processing speed can be increased by reducing the memory access time (read time and write time). Reducing memory access time is particularly effective in a system that handles a large amount of data. Examples of such systems are a speech recognition system and a picture information processing system. In a data processing system for the speech recognition system, the dynamic pattern matching (DP matching) method is generally employed. This method feature vector data is extracted from the input speech information to be recognized and employed as input patterns. Each feature vector is compared with previously stored reference patterns (standard patterns) to find a standard pattern which most closely corresponds with the input pattern to thereby recognize the input speech. The input patterns and the reference patterns are generally represented as a time series of feature vectors of speech. The feature vector includes, as its components, intensities in various frequency bands obtained by the speech frequency analysis and parameters obtained by a linear predictive analysis. For the pattern matching, it is required to obtain a distance between an input pattern vector a.sub.i at a point in time i and a standard pattern vector b.sub.j at a point of time j, i.e., d.sub.i,j, (e.g., the sum total of the differencies between the various vector components). Therefore, for obtaining one distance d.sub.i,j, it is necessary to read out two data trains a.sub.i, b.sub.j from a memory and feed these data trains into an arithmetic device. Since pattern data are generally large-capacity data (assuming that the sound voiced for one second requires eight kilobits, the sound voiced for 100 seconds requires 800 kilobits), memory devices independent of each other are employed for storing input patterns and storing standard patterns. respectively.
In general, the time required from the point of time when necessary pattern data are read out from the respective memory devices by memory access operations until the point of time when these pattern data are fed into an arithmetic device is much longer than the execution time of the arithmetic device required to execute a distance computation. Moreover, at least two data signals (an input pattern and a standard pattern) are always required for executing the distance computation. The arithmetic device cannot start the computation for obtaining a distance value until these two data signals have been received, so that the data processing of the prior art is exceedingly low in efficiency.
A major cause for the low efficiency is that the conventional memory system cannot overlap the cycle for reading out data from the memory with the cycle for computing a distance value. Moreover, if a RAM having a working area is used as a memory for storing the input pattern and the reference pattern, another cycle for writing the next new data to be used by the artithmetic device into the RAM is required, so that the data processing speed becomes lower.
Since speech recognition processing cannot be put to practical use if the response time is long from the point in time when speech is received until the point in time when the result of recognition is delivered, the data processing must be completed within a short period of time. As the number of input patterns is larger, matching takes a longer time, and as the recognition data processing speed is lower, the number of recognized words is smaller. Accordingly, the memory access speed is a significant factor to process data efficiently. However, by a conventional memory system, the arithmetic device must wait for data for long time as described above, so that a high-speed processing can not be obtained. On the other hand, the manufacture of a memory device having a high access speed has limitation in the device process technique. Therefore, the apparent access time must be reduced by improving both read-out and writing circuits in the memory system. However, if the circuit configuration is complicated by this improvement, it is difficult to form the memory device on an integrated semiconductor chip, so that a plurality of chips must be combined to form the memory system. In such a case, the critical path among the chips becomes long; hence, the memory access time becomes long. Accordingly, peripheral circuits of a memory array must be as simple as possible.